Recent progress in highly integrated semiconductor devices and thin gate insulating layers causes problems during application of gate bias, including an increase in tunnel current through an insulating layer, signal delay, and reduction of driving force.
One possible approach for suppressing problematic increase in tunnel current is employment of an insulating material having a dielectric constant of 10 or more instead of silicon oxide, which has a dielectric constant of 3.9. Attempts have been made to employ, as a candidate for such an insulating material having high dielectric constant, Al2O3, HfO2, a rare earth element oxide, for example Y2O3 and ZrO2, or a lanthanoid oxide. When such an insulating material having high dielectric constant is employed for forming a gate insulating layer, even if the length of the gate is reduced, the thickness of the gate insulating layer can be controlled to such a level that prevents tunnel current, while the capacitance of the gate insulating layer is maintained on the basis of the scaling law.
In order to reduce problematic signal delay or reduction of driving force, attempts have been made to employ, as a gate electrode material, a metallic material instead of polysilicon, which has been conventionally used. When a metallic material is employed as a gate electrode material, gate and source/drain resistance can be reduced, and signal delay in a semiconductor device can be reduced. In addition, gate depletion, which would otherwise be observed in a polysilicon electrode, does not occur, and driving force can be enhanced. When an insulating material having high dielectric constant is employed in combination with a metallic material, synergistic effects are obtained; i.e., performance of a semiconductor device can be maintained at high level, with tunnel current being reduced.
Production of a semiconductor device from such an insulating material having high dielectric constant, an insulating material of silicon oxide film or silicon nitride film, and a metallic material requires a step of selectively etching the metallic material. For example, in a process of patterning a metallic material only in a first gate region of a dual gates transistor, an insulating material having high dielectric constant and the metallic material are deposited on an insulating material, followed by a step of etching only the metallic material within a second gate region. When a conventional dry etching technique employing plasma gas is applied to this etching step, etching selectivity fails to be attained between the metallic material, the insulating material and the insulating material having high dielectric constant, and the insulating material and the insulating material having high dielectric constant undergo etching, resulting in difficulty in precise processing. Meanwhile, there has not yet been reported a technique for etching a metallic material through wet etching.
Under such circumstances, demand has arisen for a technique for selectively and efficiently etching only a metallic material while reducing corrosion to an insulating material having high dielectric constant or an insulating material of, for example, silicon oxide film or silicon nitride film (hereinafter may be abbreviated as “oxide film or nitride film”).